The present invention relates to error correction of data in a memory device, and more particularly, to an error correction circuit for a non-volatile memory device.
In semiconductor integrated memory devices, such as non-volatile memory devices, errors sometimes occur when data are written to or read from the memory devices. Sometimes errors in data storage may occur due to the physical characteristics of the memory devices. For example, in a conventional flash memory device, errors in the data stored in the flash memory may be caused by manufacturing defects or program disturbances. A program disturbance may be caused by an undesirable field turn-on in a typical conventional flash memory array during the programming of the memory gates in the conventional flash memory array. A field turn-on in the substrate region under the select gate transistor field oxide region between two memory gates on adjacent bit lines may cause one of the memory gates which is supposed to be in a program-inhibited state indicating a logic bit xe2x80x9c1xe2x80x9d to be xe2x80x9cturned onxe2x80x9d to a programmed state indicating a logic bit xe2x80x9c0xe2x80x9d. Bit errors in the data stored in a conventional non-volatile memory device may also be caused by various other factors.
In order to provide an acceptable level of reliability of data read from a conventional flash memory array, error correcting codes have been integrated into memory storage systems to correct bit errors in the data stored in the memory. Conventional error correcting codes such as block codes have been used in the error correction of data in conventional memory storage systems. For example, Hamming codes, which are within a class of conventional block codes well known to a person skilled in the art, have been used to provide single-bit error correction to preserve the accuracy of data in conventional memory storage devices.
Error checking and correction of data read from a flash memory array cause a delay from the time the data are pre-read from the memory by an error correction circuit to the time the error correction circuit enables the corrected data to be accessed externally by a host system. In order to minimize the time delay, error correction circuits have been implemented to compute the error addresses, that is, the syndrome generated by the error correcting block code, by parallel processing of the data read from the memory device. However, conventional error correction circuits with parallel processing capabilities can be very expensive to implement because of the complexity of the hardware. Parallel processing of data in the computation of the error addresses requires a large number of logic gates. For example, for every 1,000 bits of data read from the conventional flash memory device, approximately 5,000 XOR gates may be required for the parallel processing of data to minimize the delay in computing the syndrome.
Some applications may require that the cost of the memory storage system be minimized rather than the delay from the time of pre-reading the data from the memory array by the error correction circuit to the time the error correction circuit enables the corrected data to be read externally. In order to minimize the hardware cost, conventional error correction circuits and the methods have been implemented which involve serial processing of the data stored in the memory array to generate error addresses based upon a conventional error correcting block code. However, conventional serial processing may require hundreds of clock cycles of delay in the data access time before the data are read by the host system. A long time delay caused by the serial processing of the data may be unacceptable in some applications.
Therefore, there is a need for an error correction circuit and a method of error correction which are capable of reducing the cost of the hardware required for computing the error addresses compared to the hardware costs associated with the conventional parallel processing of the data read from the memory device, while reducing the data access time delay compared to the relatively long time delays resulting from the conventional serial processing of the data to generate the error addresses.
The present invention satisfies these needs. In accordance with the present invention, an error correction circuit for a memory device generally comprises:
(a) a data word byte counter;
(b) first and second data encoders capable of receiving first and second pre-read data bytes, respectively;
(c) a syndrome accumulator, coupled to the data word byte counter and the first and second data encoders, capable of generating a syndrome comprising first and second pluralities of syndrome bits;
(d) a data word byte address generator, coupled to the syndrome generator, capable of generating a plurality of data word byte address bits;
(e) a comparator, coupled to the syndrome accumulator and the data word byte address generator, capable of generating an error correction enable signal in response to comparing the first plurality of the syndrome bits with the data word byte address bits;
(f) a decoder, coupled to the syndrome accumulator, capable of decoding the second plurality of the syndrome bits to generate a plurality of decoded data input bits; and
(g) a correction enable buffer, coupled to the comparator and the decoder, capable of generating a plurality of correction bits in response to receiving the decoded data input bits and the error correction enable signal.
In an embodiment, the error correction circuit according to the present invention further comprises a multiplexer, coupled to the second data encoder, to generate a plurality of input bits for the second data encoder. In a further embodiment, the error correction circuit further comprises a syndrome latch, coupled between the syndrome accumulator and the comparator, to store the first and second pluralities of the syndrome bits. The first and second pluralities of the syndrome bits form a byte error address and a bit error address for the data word, respectively. In an embodiment, the byte error address consists of 5 higher order bits of the syndrome byte, and the bit error address consists of 3 lower order bits of the syndrome byte. The byte error address is transmitted to the comparator while the bit error address is transmitted to the decoder.
In a further embodiment, the data word byte counter is capable of generating a plurality of odd bits and a plurality of even bits of a byte count for each of the data words, and is coupled to the syndrome accumulator through first and second channels to transfer the even and odd bits from the data word byte counter to the syndrome accumulator, respectively. The data word byte counter, which counts the bytes within each data word to generate a plurality of byte ordinals for the respective bytes, rearranges the byte ordinals into a plurality of even bytes and a plurality of odd bytes. In a further embodiment, the byte ordinals are represented in a binary format comprising a plurality of counter bits, at least two of the counter bits having a binary 1. In a further embodiment, the data word byte counter is further coupled to the syndrome accumulator through a third channel which is a one-bit line for initializing the syndrome accumulator during the reading operation.
In an embodiment, each page of the memory is divided into 24 data words comprising a first group of 10 data words, a second group of 13 data words subsequent to the first group in sequence, and the last word subsequent to the second group in sequence. The first ten data words each comprise 20 data bytes and the next thirteen data words each comprise 24 data bytes. The last word comprises 16 bytes. The data word byte counter is capable of counting the data bytes of each of the data words to generate a binary count within five bits, at least two of the five bits having a binary 1. For a data word comprising a maximum of 26 data bytes of memory, five bits are sufficient to represent the byte ordinals of the twenty-six data bytes with at least two of the five bits having a binary 1.
When the error correction circuit according to the present invention is applied to the error correction of memory pages wherein each of the data bytes comprises 8 bits of data, a syndrome byte may comprise 5 byte error address bits and 3 bit error address bits, with the byte address bits being the higher order bits and the bit address bits being the lower order bits of the syndrome byte.
In an embodiment, the first and second data encoders comprise first and second block encoders, respectively, each of the block encoders capable of generating a set of coded bits and a parity bit associated with the coded bits. In a further embodiment, the first and second data encoders comprise first and second Hamming encoders, respectively, using a Hamming code. The coded bits and the parity bit generated by each Hamming encoder are transmitted to the syndrome accumulator for convolutional operations to generate the syndrome.
Furthermore, the data word byte address generator is capable of generating a data word byte address for each byte that is to be written to the memory. The data word byte address is transferred to the syndrome accumulator to generate the error address. In the page write operation, the data word byte address generator is further coupled to the syndrome accumulator through a second channel to signify to the syndrome accumulator such that a write operation is initiated when the write data word byte address is generated.
The present invention also provides a memory device which includes the error correction circuit as described above. The memory device according to the present invention roughly comprises a memory array, an error correction circuit coupled to the memory array, and an input-output multiplexer buffer coupled to the memory array and to receive the correction enable bits from the correction enable buffer in the error correction circuit. In an embodiment, the memory device according to the present invention further comprises a pre-read input-output bus coupled between the error correction circuit and the memory array. In a further embodiment, data input and output buffers are coupled to the input-output multiplexer buffer to transfer data from a data bus to the memory array and from the memory array to the data bus, respectively.
Advantageously, the error correct circuit according to the present invention reduces the delay from the time a data page is pre-read by the error correction circuit to the time the corrected data are allowed to be read externally from the data bus. Instead of requiring hundreds of cycles of delay in the data access time resulting from the conventional serial processing of the data in a conventional error correction circuit, the error correction circuit according to the present invention is able to reduce the delay in the external data access time to only about ten internal clock cycles for a memory page having a size of 512 data bytes. A further advantage Of the present invention is that it is able to reduce the cost of the memory hardware by reducing the number of logic gates required for the conventional parallel processing of the data for error correction. Therefore, the memory device and the associated error correction circuit according to the present invention are able to correct data errors more efficiently than conventional serial processing while providing a simpler and less expensive hardware structure than that required for conventional parallel processing.